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一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
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simulating a convolutional encoder
allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
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用matlab实现的TURBO码编码。编码器由两个RSC卷积编码器构成-TURBO achieved with matlab coding. RSC encoder by the two convolutional encoder constitute
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Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code.
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卷积编码器和viterbi译码器的设计与仿真-Convolutional encoder and viterbi decoder design and simulation
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卷积码的MATLAB实现，包括编码器和译码器。-Convolutional codes of MATLAB to achieve, including the encoder and decoder.
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convolenc -performs convolutional encoding
Convolutional Encoder with m shift register stages
x- input - the binary data to be encoded
input sequence can be of any length
k -constraint length
k can take any value greater than 3
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FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation-Convolutional code encoder and Viterbi decoder design
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Viterbi decoder for nonsystematic convolutional code. The encoder could be designed arbitrary through the generate matrix and parameter k. The number of row of generate matrix is output bits, and collom is constraint length. Parameter k is the number
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Convolutional Encoder Viterbi Decoder Simulation in MAtlab
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本设计选取CDMA通信系统中的接入信道部分进行仿真与分析。首先，通过学习相应的理论知识，熟悉接入信道实现的过程，对每一步的原理有了较深的理解，同时，也对MATALB软件进行熟悉和了解，对MATLAB软件中的SIMULINK部分及其内部的CDMA模块用法和参数设置进行熟悉，然后运用MATLAB软件对接入信道部分进行设计，并逐步地对各个模块进行分析、仿真与验证。目的是通过毕业设计工作熟悉现代无线通信系统的基本构成与基本工作原理，重点掌握卷积编码、块交织和码扩展等相关编码技术，并能将这些技术应用实际系
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CONVOLUTIONAL encoder
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Its a convolutional encoder with code rate of 1/2 and constraint length of 3.
i/p=1 bit
o/p=2 bits with 4 memory elements
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应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
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viterbi decoder with convolutional encoder
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将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
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卷积编码，主要是（2,1,9）卷积编码器-Convolutional coding, mainly (2,1,9) convolutional encoder
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this is a Simulation s of matlab for convolutional Encoder.
in it s result you will see plots for convolutional encoder and decoder.there is also two .jpg files that show the schematic of decoder and encoder.
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convolutional encoder in vhdl
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Convolutional Encoder using puncturing and depuncturing
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